Very Large Scale Integration VLSI

1.1 Introduction to VLSI Very Large Scale Integration (VLSI) refers to the process of creating an integrated circuit (IC) by combining millions to billions of transistors onto a single chip. Modern chips (2nm process) contain more than 10 billion transistors. VLSI design is the methodology for designing such complex chips reliably and efficiently. Classification Transistors per Die Era Examples

1.1.1 Moore's Law Moore's Law (1965, Gordon Moore): The number of transistors on an integrated circuit doubles approximately every two years, while cost per transistor halves. Has driven the semiconductor industry for 60 years. • Practical implication: Performance doubles; price halves roughly every 18-24 months • Slowdown: Physical limits (atomic scale, quantum tunneling, heat) are slowing classical Moore's Law at sub-5nm nodes • Continuation strategies: 3D stacking (chiplets, HBM memory), new materials (GaN, SiGe), new transistor structures (FinFET, GAAFET, nanosheet) 1.2 CMOS Technology CMOS (Complementary Metal-Oxide-Semiconductor) is the dominant technology for digital ICs. It uses complementary pairs of PMOS and NMOS transistors to implement logic functions.

1.2.1 MOS Transistor Operation

1.2.2 CMOS Inverter – The Basic Gate

Where:  = activity factor (0-1), C_L = load capacitance, f = clock frequency • Propagation delay: t_pHL = 0.69 × R_n × C_L (fall); t_pLH = 0.69 × R_p × C_L (rise) • Speed-power product: Lower supply voltage reduces power (V²) but increases delay • Sizing: PMOS 2-3× wider than NMOS (for same R) because hole mobility  1/2-1/3 of electron mobility 1.3 VLSI Fabrication Process (CMOS)

1.4 VLSI Design Hierarchy • System level: Architecture design; specification in C/SystemC/SystemVerilog • Register Transfer Level (RTL): Describe data flow and operations in Verilog/VHDL • Logic level: Boolean equations; gate-level netlist after synthesis • Circuit level: Transistor-level schematic with sizing; SPICE simulation • Physical/Layout level: Geometric representation; polygons on layers; DRC/LVS • Process level: Manufacturing steps; process parameters; yield 1.4.1 Design Verification Steps • DRC (Design Rule Check): Verify geometries satisfy manufacturing constraints • LVS (Layout vs Schematic): Confirm extracted netlist matches schematic • Parasitic Extraction (RC): Extract resistances and capacitances from layout • STA (Static Timing Analysis): Verify all timing paths meet setup/hold constraints • Functional simulation: RTL-level; gate-level; post-layout simulation • Power analysis: IR drop, dynamic power, thermal analysis Simplified Design Rules 2.1 Purpose of Design Rules Design rules are a set of geometric constraints that define the minimum feature sizes and spacings allowed in an IC layout for a given process technology. They ensure reliable fabrication with acceptable yield. Design rules translate process limitations into geometric constraints on the layout.

2. Simplified Design Rules

2.1 Purpose of Design Rules

Design rules are a set of geometric constraints that define the minimum feature sizes and spacings allowed in an IC layout for a given process technology. They ensure reliable fabrication with acceptable yield. Design rules translate process limitations into geometric constraints on the layout.

 

2.1.1 Why Design Rules are Needed • Lithography limitations: Diffraction limits minimum printable feature; mask misalignment causes layer-to-layer offset • Etching variations: Dry/wet etch undercutting varies; spacing must accommodate worst-case • Implant straggle: Ion implant lateral spreading; junction edges must be properly spaced • CMP non-uniformity: Chemical-mechanical polishing removes material non-uniformly; density rules needed • Electromigration: High current density in metal causes atomic migration; minimum metal widths for current capacity • Yield optimization: Larger geometries have lower defect probability but waste area 2.2 Lambda () Design Rules – Mead-Conway Approach Lambda () design rules were introduced by Carver Mead and Lynn Conway (1980) as a technology-independent, scalable design methodology. All design rule dimensions are expressed in multiples of , where  = half the minimum gate length for a given process technology.

l = L_min / 2 (half the minimum feature size)

Example: For 90nm process: L_min = 90nm, l = 45nm. For 180nm process: L_min = 180nm, l = 90nm.

2.2.1 Special Design Rules • Antenna rules: Limit area of floating poly/metal during etch to prevent gate oxide damage from charge buildup; fix with diode protection or jumpers • Density rules (fill): Each layer must have 20-80% density per unit area for CMP uniformity; use dummy metal/poly fill • Latch-up rules: Guard rings (N+ tie in N-well, P+ tie in substrate) required near NMOS/PMOS to prevent parasitic SCR triggering • Electromigration rules: Metal current density < 1mA/m (M1) to prevent atomic migration failure; wider wires for power rails • Critical area analysis (CAA): Statistical yield estimation based on defect density and critical area per layer 

2.3 Process Layers in CMOS Layout

 

Static and Dynamic Logic, Multiphase Clocking

3.1  Static CMOS Logic

Static CMOS gates maintain their output state as long as power is applied, regardless of clock. They use complementary pull-up network (PUN) of PMOS transistors and pull-down network (PDN) of NMOS transistors.

3.1.1  Complementary CMOS Design Rules

• Duality: PUN is the dual network of PDN. For every NMOS series connection, the corresponding PMOS is parallel (and vice versa)

• NAND gate: PDN = NMOS series (A AND B must both be high); PUN = PMOS parallel

• NOR gate: PDN = NMOS parallel (either A OR B high ® output low); PUN = PMOS series

• Complex gates: NAND-NOR combinations in one stage (AOI, OAI gates) reduce transistor count

• Transistor count: 2n transistors for n-input gate (n PMOS + n NMOS)

• No static power: Never a DC path from VDD to GND ® zero static power (only leakage)

• Full swing: Output always swings rail-to-rail (0 to VDD) ® maximum noise margin

 3.1.1  AOI and OAI Complex Gates

3.1.1  Ratioed Logic

• Pseudo-NMOS: PMOS always-on load + NMOS PDN; faster but has static power; ratio must satisfy noise margins

• DCVS (Differential Cascode Voltage Switch): Complementary outputs; self-timed; fast for XOR/adder functions

• CVSL (Cascode Voltage Switch Logic): Uses cross-coupled PMOS loads; evaluates both Q and Q' simultaneously

• Pass transistor logic (PTL): Use NMOS as transmission gate; simpler wiring but VT loss for NMOS passing "1"

• Transmission gate (TG): NMOS + PMOS in parallel as bilateral switch; full swing transmission; uses 2T per switch

3.1  Dynamic CMOS Logic